This invention relates to a phase comparator circuit for comparing the phase of an input signal to a reference phase for detecting a phase error of the input signal, and a phase synchronization circuit for synchronizing the phase of an output signal to that of an input signal based upon the phase error detected by the phase comparator circuit. By way of an example, the present invention relates to a phase comparator circuit and a phase synchronization circuit conveniently employed for a phase servo and a frequency servo for realizing an operation of following up with rotation of the rotary head in a rotary head type digital video tape recorder.
In a rotary head video tape recorder, the rotary phase or the rpm is locked to the phase or frequency of the input signal by a phase locked loop PLL or an automatic frequency control (APC) circuit for effecting an operation of following up with rotation of the rotary head.
In general, the PLL is made up of three components, that is a phase comparator, a loop filter and a voltage controlled oscillator (VCO). Heretofore, these components are all constituted by analog circuits. Nowadays, however, the phase comparator only is designed as a digital circuit, or additionally the loop filter is replaced by a counter for reducing the size and cost by exploiting digital techniques.
By exploiting such digital techniques, it has become possible to effect full integration and to achieve the property of maintaining the phase control information for a prolonged time. On the other hand, a novel property of stably supplying clocks even during input signal interruption has been realized and exploited in practical application.
For example, a PLL constituted by a digital circuit includes a phase comparator 100 for detecting the phase error relative to the phase of the input signal, a VCO 101 for generating clocks synchronized with the phase of the input signal based upon the phase error detected by the phase comparator 100 and a feedback counter 102 for counting down clocks from the VCO 101, as shown in FIG. 1.
The PLL also includes an integrator with limiter 103 for detecting an integration error from the phase error detected by the phase comparator 100 and the input signal phase, an adder 104 for adding the integration error obtained by the integrator 103 to the phase error detected by the phase comparator 100 and a limiter 105 for limiting the amplitude level of an addition output obtained by the adder 104.
The phase comparator 100 includes a detector 106 for detecting a synchronization signal for the input signal, a ramp generator 107 for generating a ramp signal based upon clocks of the feedback counter 102, and an error detector 108 for detecting a phase error by the ramp signal generated by the ramp generator 107 and the synchronization signal detected by the detector 106.
In FIG. 2, showing output timings of respective signals in the case where the synchronization signal frequency is higher than the ramp signal frequency, signals a, b, c, d, and e denote the synchronization signal detected by the detector 106, ramp signal generated by the ramp generator 107, phase error detected by the error detector 108, integration error obtained by the integrator 103 and the control voltage supplied to the VCO 101, respectively.
Reference is had to FIGS. 1 and 2.
The detector 106 detects the synchronization signal a from the input signal and routes it to the error detector 108 and the integrator 103.
The feedback counter 102 counts down the clocks outputted by the VCO 101 and routes the resulting clocks to the ramp generator 107. The ramp generator 107 generates the ramp signal b based upon the clocks from the feedback counter 102 and routes the resulting ramp signal to the error detector 108.
The error detector 108 detects the phase error c from the ramp signal b from the ramp generator 107 and from the synchronization signal from the detector 106 and routes the detected signal to the adder 104 and the integrator 103.
The integrator 103 integrates the phase error c from the error detector 108 by the synchronization signal a from the detector 106. The integrator 103 limits the amplitude level of the signal, obtained on integration, by a limiter, not shown, and routes the limited signal as the integration error d to the adder 104.
The adder 104 adds the phase error c from the error detector 108 and the integration error d from the integrator 103 and routes the resulting sum to the limiter 105.
The limiter 105 limits the amplitude level of the sum output from the adder 104 and routes the limited amplitude level as the control voltage e to the VCO 101.
Thus, the VCO 101 outputs clocks based upon the error voltage from the limiter 105 and routes the clocks to the feedback counter 102.
The phase 360.degree. of the feedback counter 102 is divided into "0", "1", "2" and "3", as shown in FIG. 3. Due to the high frequency of the synchronization in the input signal, transition of count values of the feedback counter 102 for the pulses 1A, 1B, 1C, . . . , 1Y of the synchronization signal a shown in FIG. 2 becomes "0", "3", "2" and "1".
In case of low frequency of the synchronization signal a, transition of count values of the feedback counter 102 for the pulses 2A, 2B, 2C, . . . , 2Y of the synchronization signal a becomes "0", "1", "2" and "3", as shown in FIG. 4.
However, the above-described PLL is constituted solely by the function of phase comparison, without having the function of frequency comparison. Thus, as shown in FIG. 4, if the input frequency exceeds the range of the oscillation frequency, the phase error repeats its positive and negative states, with the result that the VCO frequency is not fixed.
For overcoming this inconvenience, there is known a PLL having the function of frequency comparison in addition to the function of phase comparison. Basically, such PLL has an up-down counter with three levels of +, 0 and -. The up-down counter counts up with a reference comparison pulse and counts down with a feedback comparison pulse. The charge pump output of a low level, high impedance and a high level is outputted for the count values of "-", "0" and "+" of the up-down counter, respectively.
The above-described PLL having the functions of both phase comparison and frequency comparison is not in erroneous operation when the frequency of the synchronization signal f in the input signal is low and the pulse 2D is not produced, as shown in FIG. 6. However, if the frequency of the synchronization signal f in the input signal is high and the pulse 1D is not produced, as shown in FIG. 7, the PLL is in erroneous operation.